Taiwan Semiconductor Manufacturing Co. has completed development and verification of its next-generation 1.6-nanometer-class chip manufacturing process, positioning the world’s largest contract chipmaker to widen its technological lead over rival Samsung Electronics as both companies race to power the next generation of artificial intelligence hardware.

According to a report from Liberty Times, cited by ChosunBiz on Aug. 20, TSMC has finished development and validation of its angstrom-class A16 process and expects to begin mass production during the fourth quarter of 2026. The timeline aligns with TSMC’s own previously published guidance, which had pointed to volume production of the A16 node sometime in the second half of 2026, making the newly reported Q4 target a more specific milestone rather than a departure from the company’s existing roadmap.

The A16 process is being marketed as the first angstrom-class CMOS platform to feature what TSMC calls Super Power Rail technology, according to BigGo Finance. That design relocates a chip’s power delivery network to the backside of the wafer, a shift that frees up front-side routing space typically consumed by competing power and signal wiring, allowing the chip to better handle the dense computational demands of high-performance computing applications.

Compared with TSMC’s enhanced 2-nanometer N2P process, the A16 node delivers meaningful performance and efficiency gains. According to multiple outlets including Android Authority and Deal N Tech, the new process offers an 8% to 10% increase in computing speed at the same power level, or alternatively a 15% to 20% reduction in power consumption at the same computing speed, alongside an 8% to 10% increase in overall chip density. The News International’s coverage noted the same performance range, describing the A16 chips as delivering either faster computing speed or lower power draw depending on how a customer chooses to configure the tradeoff for a given application.

Notably, TSMC’s A16 process is not initially targeted at consumer smartphones. According to Android Central, the new chips are designed primarily for AI and high-performance computing applications as their main initial market, meaning the technology is unlikely to appear in phone chips in the near term. That timeline stands in contrast to the 2-nanometer chips already expected from major smartphone chipmakers including Apple, Qualcomm and MediaTek later this year, all of which remain a full node behind TSMC’s newly completed A16 process in terms of raw transistor density.

The successful completion of A16 development carries significant competitive implications given Samsung’s own recently revised chip manufacturing timeline. According to BigGo Finance, Samsung Electronics had originally announced in 2022 that it planned to begin mass production of its own 1.4-nanometer process in 2027, but the company recently revised that roadmap at the SAFE Forum 2026, pushing its 1.4-nanometer mass production target back to 2029. That revision leaves Samsung roughly one year behind TSMC’s own 1.4-nanometer A14 process, which the Taiwanese chipmaker is targeting for mass production in 2028.

Industry analysts cited by BigGo Finance suggested that Samsung’s delayed 1.4-nanometer timeline reflects a deliberate strategic choice by the company to prioritize yield improvement and capacity expansion on its existing 2-nanometer process rather than racing ahead toward more advanced nodes. With AI chip production continuing to transition from 3-nanometer to 2-nanometer manufacturing, analysts noted that focusing on optimizing and scaling up 2-nanometer output represents a more realistic near-term strategy for Samsung to secure high-value chip orders, even as TSMC continues pushing further ahead on its broader technology roadmap.

TSMC’s advancement in backside power delivery technology also places it in direct competition with Intel, which was the first chipmaker in the industry to commercialize a similar approach. According to BigGo Finance, Intel introduced its own version of backside power delivery, branded PowerVia, in its Panther Lake processor lineup, though that implementation required significant pin count adjustments, metal pitch relaxation and cell architecture redesign during development. The News International’s coverage similarly noted that while Intel has already deployed backside power delivery commercially, TSMC’s overall manufacturing scale and broader customer portfolio remain significant competitive advantages that continue to favor the Taiwanese company within the advanced chip foundry market.

Looking further ahead, TSMC’s successful A16 development is viewed by industry observers as a positive signal for the company’s subsequent A14, or 1.4-nanometer, process, which remains on track for mass production in 2028, according to BigGo Finance. Some reports have also indicated that TSMC is separately pursuing an eventual 1-nanometer manufacturing node, alongside plans to construct new “Giga Fab” manufacturing facilities in Taiwan to support that longer-term roadmap, according to earlier reporting from TweakTown. Samsung has responded to that longer-term competitive pressure by launching development of its own next-generation 1-nanometer process, which the company has internally referred to as its “dream semiconductor process,” targeting mass production by 2029, according to the same report.

Beyond the direct competitive dynamic with Samsung, TSMC’s advancement toward increasingly smaller chip manufacturing nodes also comes as IBM has separately demonstrated a sub-nanometer chip architecture that goes beyond even TSMC’s most advanced current roadmap. According to Android Authority, IBM has estimated it will take approximately five years before that more advanced sub-nanometer design becomes ready for actual production, suggesting TSMC’s newly completed A16 process and its subsequent 1.4-nanometer and eventual 1-nanometer plans remain focused on delivering the most immediately commercially viable advances within the current generation of the ongoing global chip manufacturing race.

With TSMC targeting A16 mass production for the fourth quarter of this year and Samsung continuing to focus its near-term resources on optimizing its existing 2-nanometer process rather than accelerating its own more advanced node timeline, the gap between the two chipmakers’ most cutting-edge manufacturing capabilities appears likely to persist, at least in the near term, as both companies continue competing for the lucrative and rapidly expanding market for chips powering artificial intelligence infrastructure and high-performance computing applications worldwide.