FPGAs used to be mysterious, expensive devices, but these days you can buy surprisingly capable boards for very little money. Some years ago, I did an FPGA Bootcamp over on Hackaday.io. Much of that material still applies, but the hardware is dated. So I decided it was time to update it, using the inexpensive Tang Nano 20K and its GOWIN GW2AR-18 FPGA as the main platform, with perhaps a few excursions into other FPGAs.
History and Motivation
Then one day, someone realized they could do the same thing but make the electrical connections between the blocks configurable. Maybe have fuses you can blow, or use EEPROM or RAM cells to remember which blocks are connected to which. It is complicated, sure, but then you can make many of these chips and sell them to people who could, in theory, make their own custom chips without your help.
When do you need an FPGA? A classic classroom exercise for an FPGA, for example, is a traffic light because it shows off how to do state machines, which are important for some kinds of FPGA designs. But other than as a learning example, why would you do this? Even a simple 8-bit CPU can handle a traffic light.
Suppose instead that you have hundreds of digital sensors on a rocket, and any one of them must raise an alarm within a few microseconds. A processor has to sample inputs in groups, service interrupts, or rely on extra hardware. An FPGA can simply implement the equivalent of one enormous OR gate. It watches every input continuously, and unrelated logic elsewhere in the FPGA does not steal execution time from it. Can you do it with a microcontroller? Probably, but not easily. For some classes of problems, an FPGA is the better answer.
Of course, you can also build a CPU on your FPGA and some FPGAs have CPUs in the same package. This is often a sweet spot because then things that are easy to do in software, you do in software. Things that are easier to do in hardware, you do in the FPGA.
The 20K Solution
How big of an FPGA do you need? It is hard to compare FPGAs because the blocks are different. Think of PC memory. You can talk about 1 GB vs 4 GB, but the full picture depends on the memory speed, bandwidth, and timing. FPGAs are the same way. Two FPGAs may have a similar number of building blocks, but one may have much more powerful building blocks than the other. However, the 20K board’s FPGA is quite capable, even if it is hard to compare it directly to other FPGAs from other vendors.
It uses GOWIN’s GW2AR-LV18QN88C8/I7, which contains 20,736 four-input look-up tables (LUT4s) and 15,552 flip-flops. The exact maximum clock rate depends heavily on the logic and routing, so there is no single useful “FPGA clock speed,” but the device is quite comfortable in the low hundreds of MHz for appropriately pipelined designs.
Where the chip shines is memory. Most FPGAs have distributed RAM, which eats up resources on the chip, and block RAM, which are dedicated RAM cells. The GOWIN has both of these options. It also has a separate 8 Mbyte, 32-bit SDR SDRAM right in the package. Of course, you have to eat up some FPGA resources to talk to it, but not as much as you might think, and certainly not as much as it would take to place an 8 Mbyte RAM in the FPGA fabric.
There are other special-purpose blocks, like 48 18×18 multipliers, you can configure in a few ways. The Nano 20K board also has a programmable clock generator, QSPI flash (64 Mbits), and connections for audio, LCD, microSD, and HDMI. A microcontroller lets you program the clock generator, flash the chip via JTAG, or provide a virtual serial port back to the host.
Simply FPGA
The basic workflow for an FPGA is:
- Define the logic you want using an HDL (we will use Verilog, but VHDL is also common).
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Define a “top block” that connects to the outside world.
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Set up constraints that mainly tell the device which pins connect to which ports on the top block.
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Run a synthesis process that converts your HDL to primitives.
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Run a place and route process that assigns primitives to specific chip resources and produces a “bitstream.”
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Download the resulting bitstream to the FPGA’s RAM or to the configuration flash (which makes it survive a power cycle).
You can do all of these things with GOWIN’s IDE or open-source tools that we’ll talk about later.
Inside
You might think you just want to draw schematics. Some FPGA tools allow that, but the GOWIN IDE does not. It can, however, draw schematics to show you what you asked for. Turns out, if you are doing something large, schematics are a pain. Why draw out a 7-segment decoder when you can just describe it using a software-like language?
Inside the chip, there aren’t really uncommitted gates per se. There are lookup tables. So if you specify that Z=A|(BC)|(A^D) it doesn’t really go find an AND gate, an OR gate and an XOR gate. It just develops a table and programs that table to produce that function. That’s why LUTs — Look Up Tables — are important.
Simplicity
So let’s look at the simplest possible thing you might do.
module top(output led1, output led, input sw0, input sw1); assign led=~(sw0|sw1); assign led1=~(sw0&sw1); endmodule
We’ll talk more about Verilog later, but for now note that nothing “executes” these lines one at a time. This literally tells the FPGA design software to connect the two switches to a logic gate and then invert the result and connect it to the LED. At run time, this isn’t code, it is wiring.
The LEDs on the board are active low, so this just takes two inputs (presumably switches), computes the OR and AND, and outputs them to the LEDs. The switches on the 20K are pulled down so there’s no need for a pull up or pull down in the FPGA. The output is a logic one when you press the swtich.
IO_LOC "led" 15; IO_PORT "led" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; IO_LOC "led1" 16; IO_PORT "led1" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; IO_LOC "sw1" 88; IO_PORT "sw1" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3; IO_LOC "sw0" 87; IO_PORT "sw0" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
That’s it. The schematics come in two flavors. One shows what you’d expect (see the figure). The other shows opaque LUT boxes.
The video below walks through the design from starting the project to watching it work on a breadboard.
Installing
I’m glossing over a lot of details. While the GOWIN software runs on Linux, I had to do a lot to get it to work. Since I wasn’t on a supported distro, I had to work out the dependencies myself, but that wasn’t too hard.
The problem was when I tried to execute the program. The first problem was with libfreetype.so.6. I removed the private copy and linked it to my system copy. That got me a little further. However, to get it all running, I needed to set (or add) GOWIN’s lib directory to LD_LIBRARY_PATH to prevent it from picking up system libraries.
The programmer also needed a little work to not run afoul of other drivers on the system. The specific cure there for me was to build the file: /etc/udev/rules.d/99-tang-nano-20k.rules with these lines:
SUBSYSTEM=="usb", DRIVER=="ftdi_sio", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", ATTR{bInterfaceNumber}=="00", RUN+="/bin/sh -c 'echo $kernel > /sys/bus/usb/drivers/ftdi_sio/unbind'"
Of course, my fixes may or may not help your problems. If you are lucky, you won’t need any fixes at all. The open-source tools are perhaps a little easier to deal with, and we’ll look at those too. However, some of the GOWIN tools are nice, and you can check an option to have it always use your choice of external editors, which is a nice feature.
Next Time
If you need a refresher on digital logic, the original FPGA Bootcamp 0 lets you learn about logic design using a free tool in your browser. No FPGA required at all. Meanwhile, we’ll be looking later at open-source tools, IP, synchronous logic, and using the built-in logic analyzer, among other things. If you want to talk about this series, drop by our Discord server.
When you finish up your next FPGA project, don’t forget to send us a tip. You might see your project on Hackaday.
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